DECT Sync pinout and signal details
Clear-Com uses the ETSI DECT Sync signal. Below this text is an excerpt from the spec.
Explanation of DECT sync can be found here Matrix: E-Que dect sync connections on multiple frames
The DECT sync signal appears across pins 3 and 6 of the E1 / Antennas RJ5 connector on the rear of the E-Que card
The FSII (E1) Antenna uses all 8 wires of the CAT5 cable on an E1 pin out when wired back to a splitter, base station or directly to an E-Que card.
E1 / Antenna RJ45 | Function |
---|---|
Pin 1 | TX Tip +ve |
Pin 2 | TX Ring –ve |
Pin 3 | DECT Sync +ve (For Cellcom/ FreeSpeak connection to Antenna) |
Pin 4 | RX Tip +ve |
Pin 5 | RX Ring –ve |
Pin 6 | DECT Sync –ve |
Pin 7 | GND |
Pin 8 | +12V (From base or splitter – No power from E-Que rear) |
It’s a 100 HZ pulse train with the positive pulses about 880 µs wide, and every 16th pulse is 2640 µs , three times as wide.
This same signal also appears on the dedicated DECT IN / OUT RJ45 connectors on the EQUE card / FSII Base . The dedicated DECT Sync In / OUT connectors allows the user to pass Dect sync to other stand-alone DECT matrix / basestation or 3rd party devises who maybe sharing the same RF space
The pin out for the dedicated DECT Sync IN / OUT RJ45 is
DECT Sync IN Connector |
|
---|---|
Pin 1 | DECT_SYNC_IN- |
Pin 2 | DECT_SYNC_IN+ |
Pin 3 | 8KHZ_IN+ |
Pin 4 |
|
Pin 5 |
|
Pin 6 | 8KHZ_IN- |
Pin 7 |
|
Pin 8 |
|
DECT Sync OUT Connector |
|
---|---|
Pin 1 | 8KHZ_OUT+ |
Pin 2 | 8KHZ_OUT- |
Pin 3 | DECT_SYNC_OUT+ |
Pin 4 |
|
Pin 5 |
|
Pin 6 | DECT_SYNC_OUT- |
Pin 7 |
|
Pin 8 |
|
B.2.1 Synchronization signal
The synchronization signal is a 100 Hz signal having positive pulses of width between 5 μs and1 ms, except for frame 0 (every 16th pulse), which has a pulse width between 2 ms and 5 ms. This signal establishes the10 ms DECT frame interval and the 160 ms DECT multiframe interval.
The synchronization signal shall have a long term frequency accuracy of better than ± 5 ppm (nominal conditions) or± 10 ppm (extreme conditions).
As the wave form is asymmetric, devices can establish proper timing relations in the event that the differential pair of input signal wires is (improperly) connected (pair inversion).
The random phase jitter on the falling edge of the synchronization signal shall not exceed 0,5 μs rms. The differential amplitude shall be greater than 400 mV peak to peak.
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