The Huawei CE8850 switch can be setup as Boundary clock or Transparent clock in AES67 networks
Please be aware that it requires a careful configuration up.
You will require a Huawei TAC support account in order to get access to a Huawei field application engineer for on site support
Ensure the your Huawei is running the latest and most up to date software versions |
Here is a link to Huawei CE8850 switch manual
https://support.huawei.com/enterprise/en/doc/EDOC0100523061?section=j00f https://support.huawei.com/enterprise/en/doc/EDOC0100523061?section=j00f
Extract:
12.9.1 Example for Configuring the BITS as the PTP Master Clock Source
(BITS == Building integrated Timing Supply)
The 1588v2 technology transmits clock signals on the network. If a network clock signal needs to be synchronized with the external clock source, you need to introduce the standard clock source independently.
As shown in Figure 12-8, the BITS is connected to an external GPS to advertise the input clock or time signals to the device named Master, which serves as the master clock of the bearer network and advertises the received clock or time signals to devices on the bearer network.
The BITS of the switch Master is connected to two-channel clock sources: BITS0 and BITS1. BITS0 obtains a frequency signal through Ethernet synchronization and BITS1 obtains a time signal through 1588v2. The switch synchronizes the time through Ethernet synchronization and 1588v2.
Figure 12-8 Networking diagram of configuring the BITS as the 1588v2 clock source
The configuration roadmap is as follows:
Connect Master to the BITS clock.
Configure attributes for the BITS clock.
Configure the BITS as the 1588v2 clock or time source.
To complete the configuration, you need the following data:
· BITS signal type
· Attributes of the BITS time source, including time source value
· Priority of the static clock source
Connect Master to the BITS clock source, that is, BITS0, BTS1.
Configure attributes for the input signals of the BITS clock.
<Master> system-view [Master] clock bits-type hz-2m bits0 [Master] clock priority 1 source 1 system [Master] clock manual-switch source 1 system [Master] clock bits-type 1pps-tod in bits1 [Master] ptp clock-source bits1 on |
NOTE:
The default WTR time of a clock source is 1 minute. Generally, you do not need to change the default value.
If you want to see the clock source switching result during debugging, set the WTR time to 0.
Configure attributes for the BITS clock source on
Master.
[Master] ptp clock-source bits1 time-source 2 |
NOTE:
BITS is connected to an external time source, namely, GPS, and its time-source is 2.
Enable basic 1588v2 functions on
Master and configure the device type as OC.
<Master> system-view [Master] ptp enable [Master] ptp device-type oc [Master] interface gigabitethernet 1/0/0 [Master-GigabitEthernet1/0/0] ptp delay-mechanism pdelay [Master-GigabitEthernet1/0/0] ptp enable [Master-GigabitEthernet1/0/0] quit |
Verify the configuration.
After the preceding configurations, run the display clock source command in any view on Master. You can view that BITS0 and BITS1 on Master are in Normal state, indicating that Master has successfully traced the BITS clock source.
<Master> display clock source Reference Clock Source Signal Fail S1 Byte ID SSM --------------------------------------------------------------------- 0 Inner Clock No -- - SEC 1 BITS0 No 0f - DNU 2 BITS1 Yes -- - DNU 3 Peer Board BITS0 Yes -- - DNU 4 Peer Board BITS1 Yes -- - DNU 5 Left Frame Clock Yes -- - DNU 6 Right Frame Clock Yes -- - DNU 7 FSU Yes -- - DNU 8 Peer Board FSU Yes -- - DNU 9 System Clock No -- - DNU |
Run the display clock mode command in system view on Master. You can view that Master has stepped into lock mode, which means the frequency of Master has traced the signal from BITS0 port.
<Master> system-view [Master] display clock mode QL-Enable : No. Freq-Check : No. Retrieve : Yes. Hold Type : Hold 24 hours. Run Mode : Trace.(SyncOK) Bits0 : Locked. Bits1 : Locked. System mode: Manual-switch to clock source 1: BITS0. Bits0 mode : Auto select clock source 9: System Clock. Bits1 mode : Auto select clock source 9: System Clock. Clock time : 1pps-tod time from bits1 |
After the configurations, run the display ptp all command on Master, and you can view the current operation status of 1588v2.
<Master> display ptp all Device config info ------------------------------------------------------------------ PTP state :enabled Domain value :0 Slave only :no Device type :OC Static BMC :no Local clock ID :00e0fcfffe010203 PTP freq-sync :no BMC run info ------------------------------------------------------------------ Source port :bits1 Leap :None UTC Offset :0 UTC Offset Valid :False Port info Name State Delay-mech Ann-timeout Type Domain ------------------------------------------------------------------------ GigabitEthernet1/0/0 master pdelay 9 OC 0 Clock source info Clock Pri1 Pri2 Accuracy Class TimeSrc Signal Switch Direction In-Status ------------------------------------------------------------------------ local 128 128 0x31 187 0xa0 - - - - bits0 128 128 0x20 6 0x20 none off -/- abnormal bits1 0 128 0x10 1 0x20 1pps on in/- normal |
· Configuration file of Master
· # · sysname Master · # · clock priority 1 source 1 system · clock manual-switch source 1 system · clock bits-type hz-2m bits0 · clock bits-type 1pps-tod in bits1 · # · ptp enable · ptp device-type oc · ptp clock-source bits1 clock-accuracy 10 · ptp clock-source bits1 clock-class 1 · ptp clock-source bits1 priority1 0 · ptp clock-source bits1 on · # · interface GigabitEthernet1/0/0 · ptp delay-mechanism pdelay · ptp enable # |